ECL logic modules are distinguished by particularly high speed because there is no saturation of the transistors. The principle of the circuits is based on the fact that a constant emitter current is fed to a differential amplifier each having a first and a second transistor and the base of the first of the transistors has a bias between a low and a high level. Depending on the potential of the base of the second transistor, the latter or the first transistor takes over the current which causes at the respectively associated collector resistor a voltage drop determining the output state. AND logic circuits can be realized ver simply by series-gating where several such stages are located one on top of the other, i.e., the collectors of the lowest level plane are always connected to the emitters of the differential stage belonging to the next higher potential plane, and only the topmost plane has collector resistors. In the case of OR gates, the collectors of the topmost potential plane lead to a nodal point and from there to the collector resistor.
The number of input variables in the case of AND conjunctions is limited by the number of possible series-gating stages, the levels of which differ by a diode voltage each. In order to assure a sufficient signal excursion, maximally three stages can be on top of each other, taking into consideration the required current sources with supply voltages of 4.5 to 5.2 V.
According to the state of the art, more than three input variables in an AND gate are realized by connecting in series several series-gating gates, in which respective partial interconnections are carried out. From three input variables an (auxiliary) output signal is generated which addresses an input of the next-following gate. Four input variables, for instance, require three series-gating stages of the first and two stages of the second gate as is shown in FIG. 1 by the example of a circuit of a 4-bit multiplexer with latching.
The logic function belonging to the circuit example of FIG. 1 reads: EQU Q(t)=A.B.C.D1+A.B.C.D3+A.B.C.D4+Q(t-1).C.
The maximally four input variables of the AND gates require two series-connected series-gating gates. The first gate realizes the logic function M=A.B.D1+A.B.D2+A.B.D3+A.B.D4 and the second gate, the logic function Q(t)=M.C.+Q(t-1). C. On the lowest level plane VSI there are constant-current sources I1 to I7 with their emitter resistor RI1 to RI7, supplying the circuit. The two differential amplifiers DA and DC of the lower series-gating stage with the base bias VB3 are controlled by the emitter followers TA and TC and their inputs A and C. The diodes DIA and DIC serve for matching the level to the next-higher stage with a base bias VB2 for differential stages DB1 and DB2, DM and DQ(t-1) which are controlled by the emitter followers TB, TM and T1Q(t-1) with the inputs B and M respectively and, in connection with the series base resistor RE3, by Q. Superimposed on this plane is the third series-gating stage with the differential amplifiers DE1 to DE4 and the inputs D1 to D4. The corresponding bias VB1 is present at the bases of two two-emitter transistors, the collectors of which are tied together and form an OR logic circuit in conjunction with the common collector resistor RE1. Its collector potential controls, via the transistor TM, the input M of the second series-gating gate which is connected in series and the output states Q and Q which are present at the collectors of the differential stages DM and DQ(t-1) and their load resistors RE2, RE4 and RE5 and form the output of the circuit.
Disadvantages of this method are the relatively long gate propagation times which depend on the number of the series-gating stages to be traversed and are, for instance, for the circuit according to FIG. 1, typically for the signal Di after Q 1.07 ns, for A after Q 1.33 ns and for B after Q 1.20 ns; the relatively large amount of power required due to the large amount of circuitry; and the frequently not optimal utilization of the series-gating stages.
It is an object of the invention to further increase, by circuitry measures with only two series-gating stages, the number of input variables, and to shorten the signal propagation time.